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authorVoon Weifeng <weifeng.voon@intel.com>2021-04-06 09:32:50 +0800
committerDavid S. Miller <davem@davemloft.net>2021-04-07 14:24:23 -0700
commit017d6250ad719d3ddab9070446db1e9fd4ba4a65 (patch)
treefeb970022b5575dd53ff849ed06d2c154bfab4b5 /tools/perf/scripts/python/export-to-postgresql.py
parent56f15e2cb1f77fbcf9df38de7e5dcb4b37070196 (diff)
stmmac: intel: Enable SERDES PHY rx clk for PSE
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up sequence and vice versa. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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