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authorSimon Horman <horms+renesas@verge.net.au>2018-01-17 17:17:15 +0100
committerSimon Horman <horms+renesas@verge.net.au>2018-02-12 13:50:57 +0100
commit0f2901d74a99e2e6c0aea2ef9b1820c7d0ed88e1 (patch)
tree1a877d76a367aaf76aa51bea8829ece0c5d11870 /tools/perf/scripts/python/export-to-postgresql.py
parentb190cce35ff90e392f89a3d45e0814cdbfd7434c (diff)
ARM: dts: r8a7794: add soc node
Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car Gen2 SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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