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authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>2025-03-09 21:13:58 +0000
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-04-08 10:16:09 +0200
commit20fc4ea6d7e379cd492a6fd5c060013a9ebdf3db (patch)
tree6177264e5780e0504fb9eaf4751e2ef28c7523a8 /tools/perf/scripts/python/export-to-postgresql.py
parent0af2f6be1b4281385b618cb86ad946eded089ac8 (diff)
clk: renesas: rzv2h: Refactor PLL configuration handling
Refactor PLL handling by introducing a `struct pll` to encapsulate PLL configuration parameters, ensuring consistency with the existing dynamic divider structure. Introduce the `PLL_PACK()` macro to simplify PLL structure initialization and update the `DEF_PLL()` macro to use the new `pll` structure. Modify relevant clock register functions to utilize the structured PLL data instead of raw configuration values. This refactoring improves code readability, maintainability, and alignment with the existing clock configuration approach. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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