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authorSubbaraya Sundeep <sbhatta@marvell.com>2018-11-19 18:44:32 +0530
committerBjorn Helgaas <bhelgaas@google.com>2019-04-17 15:09:01 -0500
commit2dbce590117981196fe355efc0569bc6f949ae9b (patch)
tree95b8e72f1bf42629b3eca4c52bffc375affedd6f /tools/perf/scripts/python/export-to-postgresql.py
parent9cb30a71acd45d65321c73160626f15fcdceba7a (diff)
PCI: Assign bus numbers present in EA capability for bridges
The "Enhanced Allocation (EA) for Memory and I/O Resources" ECN, approved 23 October 2014, sec 6.9.1.2, specifies a second DW in the capability for type 1 (bridge) functions to describe fixed secondary and subordinate bus numbers. This ECN was included in the PCIe r4.0 spec, but sec 6.9.1.2 was omitted, presumably by mistake. Read fixed bus numbers from the EA capability for bridges. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> [bhelgaas: add pci_ea_fixed_busnrs() return value] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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