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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-03-09 21:14:01 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-08 10:16:09 +0200 |
| commit | 360387a8f17d2cf7afd894c318df959112f377c7 (patch) | |
| tree | 099759b067c356ab731b306ce8c6ed59c94494bd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | fea942bc15135e065b456421f7a163df036242c5 (diff) | |
clk: renesas: rzv2h: Rename PLL field macros for consistency
Rename PLL field extraction macros to include the associated register name
(`CPG_PLL_CLK1` or `CPG_PLL_CLK2`) to maintain consistency with other PLL
register macros. Update all corresponding macro references accordingly.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions