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authorDan Williams <dan.j.williams@intel.com>2022-03-14 18:22:38 -0700
committerDan Williams <dan.j.williams@intel.com>2022-04-12 19:11:58 -0700
commit36bfc6ad508af38f212cf5a38147d867fb3f80a8 (patch)
treefa74756c3bed6caa3f58254e02c035a227799a1c /tools/perf/scripts/python/export-to-postgresql.py
parentfbaf2b079d2a0a9c7114fbd4d1c0f3dd7a3cb3ad (diff)
cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pci
cxl_dvsec_ranges(), the helper for enumerating the presence of an active legacy CXL.mem configuration on a CXL 2.0 Memory Expander, is not fatal for cxl_pci because there is still value to enable mailbox operations even if CXL.mem operation is disabled. Recall that the reason cxl_pci does this initialization and not cxl_mem is to preserve the useful property (for unit testing) that cxl_mem is cxl_memdev + mmio generic, and does not require access to a 'struct pci_dev' to issue config cycles. Update 'struct cxl_endpoint_dvsec_info' to carry either a positive number of non-zero size legacy CXL DVSEC ranges, or the negative error code from __cxl_dvsec_ranges() in its @ranges member. Reported-by: Krzysztof Zach <krzysztof.zach@intel.com> Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info") Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Link: https://lore.kernel.org/r/164730735869.3806189.4032428192652531946.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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