diff options
| author | Andrzej Hajda <andrzej.hajda@intel.com> | 2024-05-22 09:27:27 +0200 |
|---|---|---|
| committer | Nirmoy Das <nirmoy.das@intel.com> | 2024-05-28 14:36:05 +0200 |
| commit | 38007fa96419a9db9719f170b9e8a7877821cdd1 (patch) | |
| tree | 338ea33fcbe7809ebce3673b98a57fe85e7facf1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ce62827bc294ba5f8b3909bfa5d7dbf9de8aab6b (diff) | |
drm/xe: flush gtt before signalling user fence on all engines
Tests show that user fence signalling requires kind of write barrier,
otherwise not all writes performed by the workload will be available
to userspace. It is already done for render and compute, we need it
also for the rest: video, gsc, copy.
v2: added gsc and copy engines, added fixes and r-b tags
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1488
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240522-xu_flush_vcs_before_ufence-v2-1-9ac3e9af0323@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions