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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-30 12:41:50 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:21 +0200 |
| commit | 46bb3e15e8c7e6c045f619e91b380ff090669b83 (patch) | |
| tree | ff0e0959eea284a7b0377111c9d9ee417eab0e49 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 6cc859cae9aa8c42e8347e2806232bdffeb1b33d (diff) | |
clk: renesas: rzg2l: Add DSI divider clk support
M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
This patch add support for DSI divider clk by combining
DSIDIVA and DSIDIVB.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions