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authorJosé Roberto de Souza <jose.souza@intel.com>2022-03-30 08:57:24 -0700
committerJosé Roberto de Souza <jose.souza@intel.com>2022-03-30 13:34:46 -0700
commit47e794d69c0d8a4a1ff91fcb6e3d69bc38fcfef2 (patch)
tree2dad059d268b1c3b70bfa44937896db98db92e0f /tools/perf/scripts/python/export-to-postgresql.py
parent291f63e72e56a6433910d80e23da384c62077538 (diff)
drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pipes, leaving all pipes with a matching A_CREDIT value. While at it, also moving it to intel_pm.c as we are trying to reduce the gigantic size of intel_display.c and intel_pm.c have other MBUS programing sequences. v2: - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or when it do not needs modeset - remove the checks to wait a vblank v3: - checking if dbuf state is present in state before using it v4: - removing redundant checks - calling intel_atomic_get_new_dbuf_state instead of intel_atomic_get_dbuf_state BSpec: 49213 BSpec: 50343 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-3-jose.souza@intel.com
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