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authorSimon Horman <horms+renesas@verge.net.au>2018-01-17 17:17:03 +0100
committerSimon Horman <horms+renesas@verge.net.au>2018-02-12 13:50:56 +0100
commit4bdb7aa7dcd0cbf49298dc73adf27639bf792161 (patch)
treef1cac30afe410f03a813de47764786ba6c6936b5 /tools/perf/scripts/python/export-to-postgresql.py
parent41b3568dc4f11e555aecf37fff5a08f398f97a03 (diff)
ARM: dts: r8a7790: add soc node
Add soc node to represent the bus and move all nodes with a base address into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car Gen2 SoCs to this scheme. The ordering is derived from simply moving each node with an address up to before any nodes without a base address that occur before the soc node. To improve maintainability follow-up patches will sort subnodes of both the new soc node and the root node. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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