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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-30 12:41:56 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:21 +0200 |
| commit | 67f80edf8390fd8201bb285fe2b55df9e2e5edbe (patch) | |
| tree | a8a0881f7c42f85bb082e0439ae1e39edecaa687 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 6f6178f1e1250d959ef19f408f0e392ea29de665 (diff) | |
clk: renesas: r9a07g044: Add DSI clock and reset entries
Add DSI clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions