diff options
| author | Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2021-07-23 10:42:37 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:32:54 -0700 |
| commit | 7711749a604996a41e14b66e3163e045a89fe8e1 (patch) | |
| tree | 1f18746b185f82e886f2398c7edbe7d401241c05 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | a6a128116e55970a2df9f39e31e3c8373c0ff558 (diff) | |
drm/i915/dg2: Update lane disable power state during PSR
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions