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| author | Josua Mayer <josua@solid-run.com> | 2024-11-01 12:42:25 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2024-11-04 12:16:30 +0100 |
| commit | 8ba9d45a33c849c50053ba7b6ef4706bbb3ff709 (patch) | |
| tree | 46feddc95406bfbac63a6f4f3b7d57e467802eb2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 53857ced9f23c8720d148748fff434386780afab (diff) | |
mmc: sdhci-esdhc-imx: Implement emmc hardware reset
NXP ESDHC supports control of native emmc reset signal when pinmux is
set accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit.
Documentation is available in NXP i.MX6Q Reference Manual.
Implement the hw_reset function in sdhci_ops asserting reset for at
least 1us and waiting at least 200us after deassertion.
Lower bounds are based on:
JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159.
Upper bounds are chosen allowing flexibility to the scheduler.
Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is
still accessible after boot:
- eMMC extcsd has RST_N_FUNCTION=0x01
- sdhc node has cap-mmc-hw-reset
- pinmux set for EMMC0_RESET_B
- Linux v5.15
Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Message-ID: <20241101-imx-emmc-reset-v3-1-184965eed476@solid-run.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions