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| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2021-07-23 16:22:42 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-08-06 17:29:40 +0530 |
| commit | a69f29cb50a0069f3442c08fcf21fad55d48f4d2 (patch) | |
| tree | b9b06e53c63299e5363ef54fa957b128f5376714 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 27974e6208c0c44f89e76fc65ad67f9bc1c279a6 (diff) | |
phy: phy-mtk-tphy: add support mt8195
The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1627028562-23584-3-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions