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| author | Dillon Varone <dillon.varone@amd.com> | 2024-09-25 20:18:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-10-15 11:23:50 -0400 |
| commit | c5a332f98da56faf54d6a647d903d7272de83320 (patch) | |
| tree | 76a9f9dd25ba6dc63168157223bb2b43e3a8e7d5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 668d6808e9f23305e0eb108dbf75fc13ab344ae8 (diff) | |
drm/amd/display: resolve correct MALL size for dcn401
[WHY]
Code for dcn401 to calculate available MALL size for display was shared
with dcn32 and did not provide the correct result for all ASICs.
[HOW]
Add dcn401 specific function to properly calculate the available MALL
for display.
Reviewed-by: Chris Park <chris.park@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions