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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-05-18 16:23:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-05-23 09:06:50 +0200 |
| commit | d1c20885d3b01e6a62e920af4b227abd294d22f3 (patch) | |
| tree | 2695947f63ccc22f623fd8c13eaf4ec234f7b3a2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 7f91fe3a71aa43700eac2650e3b01d50cbbb6f48 (diff) | |
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
As per the RZ/G2L HW(Rev.1.30 May2023) manual, there are no "write enable"
bits in the CPG_SIPLL5_CLK1 register. So fix the CPG_SIPLL5_CLK register
write by removing the "write enable" bits.
Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230518152334.514922-1-biju.das.jz@bp.renesas.com
[geert: Remove CPG_SIPLL5_CLK1_*_WEN bit definitions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions