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| author | José Roberto de Souza <jose.souza@intel.com> | 2022-03-30 08:57:22 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2022-03-30 13:34:45 -0700 |
| commit | d7ade5f20e5319a2104e22c47fc414619453ca93 (patch) | |
| tree | 01fcfec56a56cc00b03314c6bdc43933de69ca2a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 1dedcdd0336c356e7ac8eb9b3bc3fe3b4faeac8d (diff) | |
drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL
MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
zeros while specification has different default values for this
registers in display 12 and newer.
While at it also converting all MBUS_DBOX macros to use REG_* macros.
BSpec: 50343
BSpec: 20231
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-1-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions