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author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | 2024-09-16 14:38:19 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2024-10-15 11:23:12 -0400 |
commit | df60dcf5b58a642e531609d0d673bb63a11ed06e (patch) | |
tree | a2d2e8cdf6cf97a1e05e87b26def080eb33ddf0b /tools/perf/scripts/python/export-to-postgresql.py | |
parent | f79f4dd6001acd1e6ea6aae8e219060a566409b2 (diff) |
drm/amd/display: Add 3DLUT FL HW bug workaround
[Why]
There is a known HW bug that causes the internal 3DLUT fetch signal to
be lost at VREADY, regardless of whether the OTG lock is being held or
not. A workaround is necessary to make sure that this internal signal
stays up after OTG unlock.
[How]
Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also
use VUPDATE_KEEPOUT to prevent lock transition in the region between
VSTARTUP and VREADY, which could cause issues with this WA sequence.
Also including misc. 3DLUT DMA-related sequence fixes to address a few
regressions causing corruption.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions