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| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2022-04-25 15:41:56 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-25 10:34:19 +0200 |
| commit | f2afa78d5a0c0b0b2461a5c532d7a84214a1b633 (patch) | |
| tree | 7b26873a761e744be488889c0f1336189b2dc789 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 90715507cb899df6c726494c0225d30130ad0cc5 (diff) | |
dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car V4H (R8A779G0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions