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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:37:51 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:37:51 +0200 |
| commit | f5684bde0375f4feb2a9ed1c146df29437652e70 (patch) | |
| tree | 5de0ff7d5fb8c5d92122091f96dfd518c9f256ce /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 576d6b40dcceade7d77e88f63e621349c6937bc3 (diff) | |
| parent | a9003f74f5a2f487e101f3aa1dd5c3d3a78c6999 (diff) | |
Merge tag 'renesas-clk-fixes-for-v6.1-tag1'
clk: renesas: Fixes for v6.1
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.
Note that HSCIF0 is used for the serial console on the White-Hawk
development board.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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