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| author | Stephen Boyd <sboyd@kernel.org> | 2022-11-22 16:47:59 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-11-22 16:47:59 -0800 |
| commit | 01e6bf9921eef8ab25586162a2b1d2ca6292b7f4 (patch) | |
| tree | 4a7d33363ca6ff1d3421c2077435c599bfa47d5b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 57d894e77237230946fe77f976a5fe8f14154824 (diff) | |
| parent | 777bcc85e1fbadfea1927e828165102cf5050b53 (diff) | |
Merge tag 'renesas-clk-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Correct the parent clocks for the (High Speed) Serial Communication
Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
Switch clocks on R-Car S4-8
- Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on R-Car
V4H
* tag 'renesas-clk-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
clk: renesas: r8a779g0: Add Z0 clock support
clk: renesas: r8a779g0: Add CMT clocks
clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
clk: renesas: r8a779f0: Fix SCIF parent clocks
clk: renesas: r8a779f0: Fix HSCIF parent clocks
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions