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| author | Eugen Hristev <eugen.hristev@collabora.com> | 2023-12-28 13:32:44 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-02-12 13:36:59 +0100 |
| commit | 09860910c589a3bb3b5268ff6f704cf6b18ada73 (patch) | |
| tree | 700326c36bc5b40600ea8293c61d2973ee3cd4eb /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 15715b602a7eb40638438e8cbfe6f9137aa67ff8 (diff) | |
arm64: dts: mediatek: mt8186: fix VENC power domain clocks
The larb clock is in fact a subsys clock, so it must be prefixed by
'subsys-' to be correctly identified in the driver.
Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231228113245.174706-6-eugen.hristev@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions