diff options
| author | Stefan Binding <sbinding@opensource.cirrus.com> | 2023-01-27 16:51:11 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-01-31 12:10:52 +0000 |
| commit | 16838bfbf6e70b7a3381ab302248bd18c085aba5 (patch) | |
| tree | c02ea2761058f5fa13b59c60378c5f75d250a173 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | e0bd53a4d1d5afa7d3a3bf46e2f0ec7940f94710 (diff) | |
ASoC: cs42l42: Wait for debounce interval after resume
Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-9-sbinding@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions