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| author | Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | 2025-08-22 11:26:37 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-09-01 13:03:31 -0500 |
| commit | 169ccd7cec9b702778ffb58a436f757db23154f2 (patch) | |
| tree | 568dc7d56c66cf3f1960d8435cc7ad22218ec63c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ad43a5317a8bda7fd9d6ad5f0b6248ba11900b44 (diff) | |
arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc
Camcc requires both MMCX and MXC rails to be powered ON to configure
the camera PLLs on SM8550 platform. Hence add MXC power domain to
camcc node on SM8550.
Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller")
Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-5-28f35728a146@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions