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| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2025-02-28 15:03:49 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2025-03-03 09:26:55 +0000 |
| commit | 1a34340ad6a4bcb0ec215d69d0f1e66e000e406e (patch) | |
| tree | 031742a4a6bb30f39f5ff9039091635622583c75 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 2014c95afecee3e76ca4a56956a936e23283f05b (diff) | |
dt-bindings: PCI: dwc: Add AMD Versal2 MDB SLCR support
Add support for MDB System Level Control and Status Register (SLCR)
aperture that is only supported for AMD Versal2 devices.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250228093351.923615-2-thippeswamy.havalige@amd.com
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions