diff options
| author | Sheetal <sheetal@nvidia.com> | 2025-05-12 05:17:42 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-05-22 11:02:08 +0100 |
| commit | 1fb500476f609008ee1c499540af32c4fa5a19de (patch) | |
| tree | 6aa1a5793915fc8304bdb4592cf226133df4dbae /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | fa83757df3f40c05b5ab4154253e8aeefa31a9a6 (diff) | |
ASoC: tegra: Update PLL rate for Tegra264
The PLLs should be set with a VCO frequency in the 900MHz – 1GHz range
to minimize jitter and ppm error for Tegra264. Add the PLLA rate
accordingly.
Therefore, use 983040000 frequency is for multiple of 8K frequencies
and 993484800 frequency is for multiple of 11.025K frequencies.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-7-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions