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| author | Cruise Hung <Cruise.Hung@amd.com> | 2022-09-08 22:04:09 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-09-21 17:27:34 -0400 |
| commit | 20c6168b3c8aadef7d2853c925d99eb546bd5e1c (patch) | |
| tree | e47cd871b1f81c8af2d0f01005db9521bbf9835d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 72002056f771a025a2e6b4578aeb538799cb9ba2 (diff) | |
drm/amd/display: Fix DP MST timeslot issue when fallback happened
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions