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| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-12-13 19:55:34 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-21 16:03:26 -0800 |
| commit | 32cae024f7186e60cbdeb5b594eb920036f38225 (patch) | |
| tree | 60c329621e6f73ada01bf8288db2232bb0810d01 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | df964016490b2cf630b1b926a1d5c610833aaa84 (diff) | |
clk: qcom: ipq8074: fix missing GPLL0 divider width
GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions