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| author | Alexis Lothoré <alexis.lothore@bootlin.com> | 2023-05-29 10:02:43 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2023-05-30 23:54:33 -0700 |
| commit | 3ba89b28adb21a5d5d78e905e2c3972816606bb4 (patch) | |
| tree | 9ccd20c4f476d44e77b5580c2550c515e4475442 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7a2dd00be869f0bcdcb13f4272913ba7371ab583 (diff) | |
net: dsa: mv88e6xxx: add field to specify internal phys layout
mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)
Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions