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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2024-09-28 11:29:55 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-07 10:43:50 +0200 |
| commit | 43a576ac8442b4c802d9228bf24b7f6388f978de (patch) | |
| tree | 247ac2e832a651cac2fd0b8ad3c3fe36195d20d3 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 9faf2a34c2e6360c37e47deaa51110c4fd3e9f4d (diff) | |
ARM: dts: renesas: r7s72100: 'bus-width' is a board property
Do not set 'bus-width' in the SoC-include DTSI. It must be set in the
board DTS file. No regressions because MMCIF was not enabled yet for
this SoC.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240928092953.2982-7-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions