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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2025-08-22 17:56:54 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-09-01 13:03:32 -0500 |
| commit | 458de584248a5630878ed11ea23188f6007036b2 (patch) | |
| tree | 3037611483f13b58c01a832394e4218579c989e3 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 35f549fcf5f1d99997cd865170fd7cb1bb66c1d7 (diff) | |
arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi
The connection between the QMP Combo PHY and the DisplayPort
controller is fixed in SoC, so move the data-lanes properties
in the SoC dtsi.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-6-5363acad9e32@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions