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authorBen Widawsky <ben.widawsky@intel.com>2022-01-23 16:29:00 -0800
committerDan Williams <dan.j.williams@intel.com>2022-02-08 22:57:27 -0800
commit46c6ad27625ca00f59903585e41667d7a45b4eb8 (patch)
treeeac5e89860506996166b67edfd10b7e002313196 /tools/perf/scripts/python/export-to-sqlite.py
parent4f195ee73ade1adf8326e5ed5fb271da51778991 (diff)
cxl: Flesh out register names
Get a better naming scheme in place for upcoming additions. By dropping redundant usages of CXL and DVSEC where appropriate we can get more concise and also more grepable defines. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Link: https://lore.kernel.org/r/164298414022.3018233.15522855498759815097.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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