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| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 17:28:22 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 18:04:49 +0100 |
| commit | 56fd27b31f1a216623f285bb77b4bcb6129e84c2 (patch) | |
| tree | 8bad50beb11b3a32a70a853e23c9203311b333cf /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 204c85d124bd51c0b1c70f1d6b0d853389179d38 (diff) | |
clk: tegra: pll: Change misc_reg count from 3 to 6
New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions