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authorGiulio Benetti <giulio.benetti@micronovasrl.com>2021-01-14 09:17:32 +0100
committerMaxime Ripard <maxime@cerno.tech>2021-01-14 12:37:28 +0100
commit67f4aeb2b41a0629abde3794d463547f60b0cbdd (patch)
treed1853d0d61f8e2a38ece09e9a246f87eda8abadc /tools/perf/scripts/python/export-to-sqlite.py
parent657b65058b1ef10578238327d84f42c0e11fb089 (diff)
drm/sun4i: tcon: fix inverted DCLK polarity
During commit 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_* macros have been changed to avoid ambiguity but just because of this ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning _SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but instead of swapping phase values, let's adopt an easier approach Maxime suggested: It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes things really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE as bit 26 and activating according to bus_flags the same way it is done for all the other signals polarity. Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") Suggested-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210114081732.9386-1-giulio.benetti@benettiengineering.com
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