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| author | Manasi Navare <manasi.d.navare@intel.com> | 2019-03-19 15:18:47 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2019-03-21 12:57:32 -0700 |
| commit | 69903dfae0310afe8a15f5cd4e376ebb7c6da1d2 (patch) | |
| tree | 3bf0c02e33933aec9a7cd4f0857b10c9100d1ee0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 76444b6e62edd73abee11e5809a960b39e00e238 (diff) | |
drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
to correctly do the left shifting to set the port sync
master select correctly.
I have tested this fix on ICL.
Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers")
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190319221847.21311-1-manasi.d.navare@intel.com
(cherry picked from commit 7264aebb81d15aa6bbed650c816bba90f026bc35)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions