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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2025-02-04 14:40:04 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-06 11:57:52 +0100 |
| commit | 79982cbac896768c3860c241df2028c3e75f5a6b (patch) | |
| tree | fe837eecdc1c1056d9843881d36c69a59423e6bf /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 81dde32e7266e7132076b886337bd29b4648e542 (diff) | |
dt-bindings: display: vop2: Add optional PLL clock properties
On RK3588, HDMI PHY PLL can be used as an alternative and more accurate
pixel clock source for VOP2 video ports 0, 1 and 2.
Document the optional PLL clock properties corresponding to the two HDMI
PHYs available on the SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20250204-vop2-hdmi0-disp-modes-v3-1-d71c6a196e58@collabora.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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