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| author | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-08-26 19:53:20 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2024-08-31 15:17:04 +0300 |
| commit | 867bf1923200e6ad82bad0289f43bf20b4ac7ff9 (patch) | |
| tree | 89d20b305c7a5b9a0bdce56181b9987cf2554087 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d355c895fa4ddd8bec15569eee540baeed7df8c5 (diff) | |
ARM: dts: microchip: sama7g5: Fix RTT clock
According to datasheet, Chapter 34. Clock Generator, section 34.2,
Embedded characteristics, source clock for RTT is the TD_SLCK, registered
with ID 1 by the slow clock controller driver. Fix RTT clock.
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Link: https://lore.kernel.org/r/20240826165320.3068359-1-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions