diff options
| author | Jouni Högander <jouni.hogander@intel.com> | 2025-07-22 15:56:18 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-07-23 09:13:27 +0300 |
| commit | 8921dce70d46e3156b5a0b21675f5ac90903d81d (patch) | |
| tree | 45e3eca6d5aa41561f85267a44e17958797c46a8 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | cf433f94f188782166598300c4c05274fd13c5a7 (diff) | |
drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read
According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.
v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes
Bspec: 68962
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions