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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2025-02-24 13:11:17 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2025-02-26 11:59:49 +0100 |
| commit | 9d245214b683e9e4fe2d5c588691337b22c48841 (patch) | |
| tree | 56015454229b3ea6c9eb62c3ca086d8ef1f3348f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 0edaa4593efe9377b4536211f9bc3812e3e53315 (diff) | |
dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC
Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
- The TINT register base offset is 0x800 instead of zero.
- The number of supported GPIO interrupts for TINT selection is 141
instead of 86.
- The pin index and TINT selection index are not in the 1:1 map
- The number of TSSR registers is 16 instead of 8
- Each TSSR register can program 2 TINTs instead of 4 TINTs
Hence add the new compatible string "renesas,r9a09g047-icu" for RZ/G3E SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20250224131253.134199-2-biju.das.jz@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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