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| author | Imre Deak <imre.deak@intel.com> | 2025-08-11 11:01:51 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-08-12 12:31:44 +0300 |
| commit | afc4e84388079f4d5ba05271632b7a4d8d85165c (patch) | |
| tree | 8792c38a2bcd77e93724c8b4bd812292a4cfb5fe /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 33cf70bc0fe760224f892bc1854a33665f27d482 (diff) | |
drm/i915/lnl+/tc: Use the cached max lane count value
Use the cached max lane count value on LNL+, to account for scenarios
where this value is queried after the HW cleared the corresponding pin
assignment value in the TCSS_DDI_STATUS register after the sink got
disconnected.
For consistency, follow-up changes will use the cached max lane count
value on other platforms as well and will also cache the pin assignment
value in a similar way.
Cc: stable@vger.kernel.org # v6.8+
Reported-by: Charlton Lin <charlton.lin@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250811080152.906216-5-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions