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| author | Aditya Swarup <aditya.swarup@intel.com> | 2019-01-10 15:08:44 -0800 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-01-15 11:47:01 +0200 |
| commit | b14c06ec024947eaa35212f2380e90233d5092e0 (patch) | |
| tree | 1936212cdef560aac5dfc8344ce231489191b65a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8cd999181f8c744c87fb64e7b3600876ec3428b2 (diff) | |
drm/i915/cnl: Fix CNL macros for Voltage Swing programming
CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.
v2: Jani suggested to keep the macros organized semantically i.e., by
function, secondarily by port/pipe/transcoder.->(dw, port)
Fixes: 4e53840fdfdd ("drm/i915/icl: Introduce new macros to get combophy registers")
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190110230844.9213-1-aditya.swarup@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions