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authorBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:14:48 -0500
committerBjorn Helgaas <bhelgaas@google.com>2025-03-27 13:14:48 -0500
commitb79789646edea60bbd089a31ab9a467933859cfd (patch)
tree04c21e86180858530bb89532140a0fcf445f4d70 /tools/perf/scripts/python/export-to-sqlite.py
parentc51638f15ef57908815b5c079bd4fc1ed8a13c00 (diff)
parent2d72d81caccad516ece9f91f86ac65ff1f2c68a2 (diff)
Merge branch 'pci/controller/brcmstb'
- Add missing of_node refcount release after of_parse_phandle() (Stanimir Varbanov) - Add BCM2712 MSI-X DT binding and interrupt controller drivers (Stanimir Varbanov) - Add brcmstb softdep on irq_bcm2712_mip MIP MSI-X interrupt controller driver to ensure that it is loaded first (Stanimir Varbanov) - Add struct brcm_pcie pointer to pcie_cfg_data so we can reference the pcie_cfg_data directly instead of copying it to brcm_pcie (Stanimir Varbanov) - Expand inbound window map to 64GB so it can accommodate BCM2712 (Stanimir Varbanov) - Add BCM2712 support and DT updates (Stanimir Varbanov) - Apply link speed restriction before bringing link up, not after (Jim Quinlan) - Update Max Link Speed in Link Capabilities via the internal writable register, not the read-only config register (Jim Quinlan) - Handle regulator_bulk_get() error to avoid panic when we call regulator_bulk_free() later (Jim Quinlan) - Disable regulators only when removing the bus immediately below a Root Port because we don't support regulators deeper in the hierarchy (Jim Quinlan) - Consistently use config access index/data register offsets from the SoC-specific pcie_offsets[] table (Jim Quinlan) - Update MDIO register fields that reduced CMD from 12 bits to 1 and widened PORT from 4 bits to 5 and split it into two parts (Jim Quinlan) - Make const read-only arrays static (Colin Ian King) * pci/controller/brcmstb: PCI: brcmstb: Make const read-only arrays static PCI: brcmstb: Make irq_domain_set_info() parameter cast explicit PCI: brcmstb: Make two changes in MDIO register fields PCI: brcmstb: Use same constant table for config space access PCI: brcmstb: Fix potential premature regulator disabling PCI: brcmstb: Fix error path after a call to regulator_bulk_get() PCI: brcmstb: Do not assume that register field starts at LSB PCI: brcmstb: Use internal register to change link capability PCI: brcmstb: Set generation limit before PCIe link up PCI: brcmstb: Add BCM2712 support PCI: brcmstb: Expand inbound window size up to 64GB PCI: brcmstb: Reuse pcie_cfg_data structure PCI: brcmstb: Add a softdep to MIP MSI-X driver irqchip: Add Broadcom BCM2712 MSI-X interrupt controller dt-bindings: PCI: brcmstb: Update bindings for PCIe on BCM2712 dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings PCI: brcmstb: Fix missing of_node_put() in brcm_pcie_probe()
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