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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2022-11-02 10:10:45 -0700 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2022-11-07 11:03:45 -0800 |
| commit | c07ee636901d1496caf81594f90fc68e9a9c7ba5 (patch) | |
| tree | 295f07c267967df09ab37f8557163e100f6255c9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | c9c12ba72e740e3adb5a2287f6d0372fa45721c3 (diff) | |
drm/i915/mtl: add GSC CS interrupt support
The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.
v2: clean up the if statement for the engine irq (Tvrtko)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221102171047.2787951-4-daniele.ceraolospurio@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions