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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:10:09 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2020-07-13 11:56:23 -0700 |
| commit | c5d3d3cf00d5ed74359e71f7b5d003cf34ba014c (patch) | |
| tree | 3abee2f7d1382a6c2ffcb43cbbe04afa879ca161 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | aecc72b14d11327804f7ca1fc76ca88a22cc1136 (diff) | |
ARM: dts: meson8m2: add resets for the power domain controller
The Meson8m2 SoCs has introduced additional reset lines for the VPU
compared to Meson8. Also it uses a slightly different VPU clock
frequency compared to Meson8 since it can now achieve 364MHz thanks to
the addition of the GP_PLL.
Add the reset lines, VPU clock configuration and update the compatible
string so the implementation differences can be managed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions