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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-06-04 18:37:10 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-06-05 18:56:53 +0200 |
| commit | d011c022efe275791897668aa421e2db9f2e6450 (patch) | |
| tree | dce8997e10145f0be97b8a52cd4fa2e90bfaf0b9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 372487b295557b6c0c7ba3583fb34a65c574ff9f (diff) | |
irqchip/renesas-rzg2l: Add support for RZ/Five SoC
The IX45 block has additional mask registers (NMSK/IMSK/TMSK) compared
to the RZ/G2L (family) SoC.
A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function
pointers for irq_[un]mask() and irq_[dis|en]able() handle the ([un]masking
of the interrupts. The irq_chip pointer is now passed as an init callback
and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240604173710.534132-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions