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| author | Stefan Agner <stefan@agner.ch> | 2018-09-04 22:21:08 -0700 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2019-03-18 11:42:13 +0200 |
| commit | d23286ff3d79e1b78b4a4b030a62c3ddc120c607 (patch) | |
| tree | 82ab6d317f67404350d4359f62cf893f1cd67df4 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 88bc4178568b8e0331143cc0616640ab72f0cba1 (diff) | |
drm/bridge: use bus flags in bridge timings
The DRM bus flags convey additional information on pixel data on
the bus. All current available bus flags might be of interest for
a bridge. Remove the sampling_edge field and use bus_flags.
In the case at hand a dumb VGA bridge needs a specific data enable
polarity (DRM_BUS_FLAG_DE_LOW).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions