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authorMika Kahola <mika.kahola@intel.com>2023-06-09 15:21:30 +0300
committerJouni Högander <jouni.hogander@intel.com>2023-06-15 12:50:32 +0300
commitd4b62a1a251db33a453ffa9d3535bf6f4a011546 (patch)
treec733b6af59cb2bea30daf25a1dc77f87e8300c82 /tools/perf/scripts/python/export-to-sqlite.py
parentb3e4aae612eca42950c4612f80ec199c15d2fd51 (diff)
drm/i915/mtl: Cleanup usage of phy lane reset
From PICA message bus we wait for acknowledgment from read/write commands. In case of an error, we reset the bus for the next command. Current implementation ends up resetting message bus twice in cases where error is not the timeout. Since, we only need to reset message bus once, let's move reset to corresponding timeout error and drop the excess reset function calls from read/write functions. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609122130.69794-1-mika.kahola@intel.com
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