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| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2025-01-14 19:30:04 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-03 11:07:05 +0100 |
| commit | d871a94062a3a32510b503df58ed60fd86f2b14f (patch) | |
| tree | f41582952954ca568cbaf49d1d44f8b5dfe34e87 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 3b0016a613e5256ef3a782286b05c7f549908ad1 (diff) | |
clk: renesas: r8a779g0: Add ISP core clocks
Add the ISP core modules clock for Renesas R-Car V4H.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions