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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-09-27 14:57:37 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-01 14:19:29 +0200 |
| commit | ddda5046e484d881563a6ad8da77f23f39f9e298 (patch) | |
| tree | de3e34d0fb32ebd581df533ee8ffcb83654c2ebd /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 25e289d0622a40a76a1bb1d5972d250bf746f8bf (diff) | |
ARM: dts: renesas: rskrza1: Enable watchdog timer
Enable the Watchdog Timer (WDT) on the Renesas RSK+RZA1 development
board equipped with an RZ/A1H SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/fe72fb72acde4f5d9f8bd1a012435519592bd2bc.1727441772.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions