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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-10-06 21:04:50 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-12-07 13:22:36 +0100 |
| commit | ec9e80ae1719de541c719116a1ca0a0c70e9240c (patch) | |
| tree | bbfdb6e1afde22fe228229e8400c1361944a396b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | af728d7ae20483add9f8d3c81280dc6298a0aa2e (diff) | |
mmc: renesas_sdhi: add quirk for broken register layout
Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions